Introduction: The sooner the signal integrity (SI) problem is solved, the higher the efficiency of the design, thus avoiding the need to increase the termination of the device after the PCB design is completed. This paper introduces several solutions to the problem of signal integrity (SI) method.

1 before the preparation of the preparatory work
Before the design begins, you must first think and determine the design strategy, so as to guide such as the choice of components, process selection and circuit board production cost control and so on. In the case of SI, research should be conducted in advance to formulate planning or design criteria to ensure that the design results do not exhibit significant SI problems, crosstalk or timing issues.

2 circuit board stack
Some project teams have a lot of autonomy to determine the number of PCB layers, while others do not have this autonomy, so it is important to know where you are.

Other important issues include: What is the expected manufacturing tolerance? What is the expected insulation constant on the circuit board? What is the allowable error for line width and spacing? What is the allowable error for the thickness and spacing of the ground plane and the signal layer? All of this information can be used in the pre-wiring phase.

According to the above data, you can choose to cascade. Note that almost every PCB that is inserted into other boards or backplanes has a thickness requirement, and that most circuit board manufacturers have a fixed thickness requirement for the different types of layers that can be made, which will greatly constrain the number of final stacks The You may want to work closely with the manufacturer to define the number of layers. The impedance control tool should be used to generate the target impedance range for the different layers. It is important to take into account the manufacturer's manufacturing tolerances and the proximity of the wiring.

In the ideal case of signal integrity, all high-speed nodes should be routed inside the impedance control (eg stripline). To optimize the SI and to keep the circuit board decoupling, the ground plane / power plane should be laid in pairs as much as possible. If you can only have a pair of ground plane / power layer, you will only be on the. If there is no power layer at all, by definition you may encounter SI problems. You may also encounter a situation in which it is difficult to simulate or simulate the performance of the board before the return path of the undefined signal is defined.

3 crosstalk and impedance control
The coupling from the adjacent signal lines will cause crosstalk and change the impedance of the signal line. The coupling analysis of adjacent parallel signal lines may determine the "safety" or the expected spacing (or parallel wiring length) between the signal lines or between the various signal lines. For example, if you want to limit the crosstalk of the clock to the data signal node within 100mV, keep the signal traces parallel, and you can find the minimum permissible spacing between the signals on any given wiring layer by calculation or simulation. Also, if the design contains nodes with important impedance (or a clock or dedicated high-speed memory architecture), you must place the wiring on a layer (or layers) to get the desired impedance.

4 important high-speed nodes
Delay and delay are the key factors that clock routing must consider. Because the timing requirements are strict, such nodes usually have to use the terminating device to achieve the best SI quality. These nodes are pre-determined and the time required to adjust the components to be placed and routed is planned to adjust the pointer to the signal integrity design.

5 technical options
Different drive technologies are suitable for different tasks. Is the signal point-to-point or a little more tap Is the signal output from the board or on the same circuit board? What is the allowable delay and noise margin? As a general guideline for signal integrity design, the slower the conversion speed, the better the signal integrity. 50MHZ clock with 500PS rise time is no reason. A 2-3NS slew rate control device is fast enough to ensure SI quality and help solve issues such as output synchronous switching (SSO) and electromagnetic compatibility (EMC).

In the new FPGA programmable technology or user-defined ASIC, you can find the superiority of drive technology. With these custom (or semi-custom) devices, you have a lot of room to select the drive amplitude and speed. At the beginning of the design, meet the FPGA (or ASIC) design time requirements and determine the appropriate output options, if possible, including pin selection.

In this design phase, from the IC supplier to get the appropriate simulation model. In order to effectively cover the SI simulation, you will need an SI simulation program and the corresponding simulation model (possibly the IBIS model).

Finally, you should create a series of design guides in the pre-routing and routing phases, including target layer impedance, wiring spacing, preferred device technology, important node topology, and termination planning.