First, the information input stage
1. Whether the information received on the process is complete (including: schematic, *. Brd file, bill of materials, PCB design instructions and PCB design or change requirements, standardized requirements description, process design documentation)
2. Verify that the PCB template is up-to-date
3. Verify that the location of the template is correct
4. PCB design instructions and PCB design or change requirements, standardization requirements that is clear
5. Confirm that the cloth on the outline drawing and the wiring area are on the PCB template
6. Compare the outline drawing to confirm that the dimensions and tolerances of the PCB are correct and that the metallized and non-metallized holes are accurate
7. confirm the PCB template is correct after the best lock the structure of the file, so as not to misuse the mobile location
Second, after the layout check stage
A. Device inspection
8, to confirm whether all the device package is consistent with the company unified library, whether the package has been updated (with viewlog check the results of the operation) If not, must update Symbols
9, motherboard and daughter board, veneer and backplane, confirm the signal corresponding to the location of the corresponding, the direction of the connector and the screen logo is correct, and the sub-board anti-mishua measures, sub-board and motherboard devices should not interfere
10, whether the components are placed 100%
11, open the device TOP and BOTTOM layer of the place-bound, see whether the overlap caused by the DRC is allowed
12, Mark point is sufficient and necessary
13, heavier components, should be placed near the PCB support point or support side to reduce the PCB warpage
14, with the structure of the device after the cloth is best to lock, to prevent misuse of mobile location
15, crimp socket around the 5mm range, the front does not allow a height above the crimp socket height of the components, the back does not allow components or solder joints
16, to confirm whether the device layout to meet the technical requirements (focus on BGA, PLCC, patch socket)
17, metal shell components, with particular attention not to meet with other components, to leave enough space
18, interface-related devices placed as close as possible to the interface, backplane bus driver as close as possible to the backplane connector
19, wave soldering surface of the CHIP device has been converted into wave soldering package,
20, whether the manual solder joints more than 50
21, the axle on the PCB into the higher components, should be considered horizontal installation. Stay out of space. And consider a fixed way, such as a fixed pad of crystal
22, need to use the heat sink device, confirm that there is enough spacing with other devices, and pay attention to the height of the main device in the range of heat sink
B. Functional check
23, digital-analog mixed-panel digital circuit and analog circuit device layout is separated, the signal flow is reasonable
24, A / D converter cross-modulus partition placed.
25, the clock device layout is reasonable
26, high-speed signal device layout is reasonable
27, the termination of the device has been properly placed (source matching string should be placed on the drive side of the signal; the middle of the string in the middle of the matching; terminal matching string should be placed on the receiving side of the signal)
28, IC device decoupling capacitor number and location is reasonable
29, the signal line to different levels of the plane as a reference plane, when the plane across the plane, the connection between the reference plane is close to the signal alignment area.
30, the protection circuit layout is reasonable, is conducive to segmentation
31, whether the fuse of the board power supply is placed near the connector and there is no circuit element in front
32, confirm the strong signal and weak signal (power difference 30dB) circuit separately layout
33, whether to follow the design guide or refer to the successful experience of the device may affect the impact of EMC experiments. Such as: panel reset circuit to be closer to the reset button
C. Fever
34, the heat-sensitive components (including liquid dielectric capacitors, crystal) as far as possible away from high-power components, radiators and other heat sources
35, whether the layout to meet the thermal design requirements, cooling channels (according to process design documents to implement)
D. Power supply
36, whether the IC power supply distance IC too far
37, LDO and the surrounding circuit layout is reasonable
38, the module power supply and other surrounding circuit layout is reasonable
39, the overall layout of the power supply is reasonable
E. Rule settings
40, whether all the simulation constraints have been correctly added to the Constraint Manager
41, whether the physical and electrical rules are set correctly (note the power network and the ground network constraints set)
42, Test Via, Test Pin spacing is sufficient
43, the thickness of the stack and whether the program meets the design and processing requirements
44, all differential impedance required for characteristic impedance has been calculated and controlled by rules
Third, after the wiring inspection phase
E
45, digital circuits and analog circuit alignment is separated, the signal flow is reasonable
46, A / D, D / A and similar circuits if the division of the ground, then the signal line between the two lines from the bridge between the two places (differential line exception)?
47, the signal lines that must cross the gap between the split power supplies should refer to the complete ground plane.
48, if the use of stratigraphic design partition is not divided, to ensure that digital signal and analog signal partition wiring.
F. Clock and high speed parts
49, the impedance of the high-speed signal lines are consistent
50, high-speed differential signal lines and similar signal lines, whether equal length, symmetrical, near parallel to the line?
51, confirm the clock line as far as possible in the inner layer
52, to confirm the clock line, high-speed line, reset line and other strong radiation or sensitive lines have been as far as possible according to the principle of 3W wiring
53, clock, interrupt, reset signal, 100 megahertz / gigabit Ethernet, high-speed signal is no bifurcation test point?
54, LVDS and other low-level signal and TTL / CMOS signal between the best to meet the 10H (H for the signal line from the reference plane height)?
55, the clock line and high-speed signal line is to avoid crossing the through hole through the hole area or device pin between the alignment?
56, the clock line has been met (SI constraints) requirements (clock signal alignment is done less hit the hole, the line is short, the reference plane continuous, the main reference plane as far as possible GND; if the layer change when the GND main reference plane Layer, within the range of 200mil from the hole is GND through the hole) if the layer change when the different levels of the main reference plane, within 200mil from the hole within the decoupling capacitor)
57, differential pairs, high-speed signal lines, all types of BUS has been met (SI constraints) requirements
G.EMC ​​with reliability
58, for the crystal, whether in its next layer of cloth? Did you avoid the signal line crossing between the device pins? For high-speed sensitive devices, is it possible to avoid crossing the signal lines from the device pins?
59, the board signal line can not have an acute angle and right angle (generally 135 degrees angle continuous turn, the RF signal line is best to use circular or after the calculation of the corner after the copper foil)
60, for the double panel, check whether the high-speed signal line and its return ground close together wiring; for multi-layer board, check whether the high-speed signal line as close as possible to the ground plane
61, for the adjacent two-layer signal alignment, as far as possible vertical alignment
62, to avoid the signal line from the power module, common mode inductors, transformers, filters under the crossing
63, try to avoid high-speed signal on the same layer of long-distance parallel alignment
64, edge of the board there are digital, analog ground, the protection of the edge of the division of the edge of the shield? Are multiple ground planes connected with vias? Is the via distance less than 1/20 of the highest frequency signal wavelength?
65, the surge suppression device corresponding to the signal line is short and thick in the surface?
66, to confirm the power, the formation of no island, no large slot, no through the hole isolation disk is too large or dense hole caused by the longer ground plane cracks, no slender and narrow channel phenomenon
67, whether the signal line across the more places, placed the ground through (at least two ground plane)
H. Power and ground
68, if the power / ground plane is divided, try to avoid the split on the reference plane has a high-speed signal across.
69, to confirm the power, ground can carry enough current. The number of vias to meet the load requirements, (estimation method: outer copper thickness 1oz 1A / mm line width, the inner layer 0.5A / mm line width, short-term current doubled)
70, for the special requirements of the power supply, whether to meet the requirements of the pressure drop
71, in order to reduce the plane of the edge of the radiation effect, in the power layer and the ground to try to meet the 20H principle. (The conditions allowed, the power layer of the indentation as possible).
72, if there is to split, split the ground does not constitute a loop?
73, the adjacent layer of different power plane is to avoid the overlap placed?
74, protection, -48V and GND isolation is greater than 2mm?
75, -48V ground is only -48V signal back, no sink to other places? If you can not, please explain the reason in the remarks column.
76, near the connector with the panel is 10 ~ 20mm protective cover, and double-row staggered hole will be connected to each layer?
77, the power line and other signal line spacing distance to meet the safety requirements?