High-speed circuit design field, there is a almost reasonable understanding of the wiring, that is, "equal length" alignment, that the alignment as long as the length of the demand must meet the timing, there will be no timing problems. In this paper, the interconnection timing of commonly used high-speed devices is established, and a general timing analysis formula is given. In order to reflect the specific analysis of the specific principles, to avoid the formula as a universal formula, the text gives the MII, RMII, RGMII and SPI case analysis. In the case analysis, two methods of formula analysis and theoretical analysis are used to prove the limitation of the formula and the advantages and disadvantages of the two methods. At the end of this paper, based on these examples, the general principles of wiring such as SDRAM and DDR SDRAM are given.

This article through examples to illustrate the key to the timing analysis is: the specific understanding of the basis of a thorough basis, the specific analysis of specific issues can not blindly apply the formula, but not through the alignment of the equal length to solve the problem of timing.

1. Typical high-speed device interconnection timing model

Figure 1 shows a simplified model of the common high-speed device interconnect interface. In the figure, the left dashed box indicates the host side of both communication devices. Common practical situations are: SDRAM controller, SPI main controller and so on. With the appropriate evolution, it is easy to get the TX group model of I2C master, MII interface, RMII shared clock model and interconnection model of DDR control signal and address signal based on this model. The right dashed box represents the passive end of the communication. In this model, the data is bidirectional, but the clock is a single direction. Simply put, that is, a single direction of the clock to send, two-way data transmission. This feature is the adaptation of this model.
High Speed ​​Circuit Design _ Simplified Device Interconnection Model
Figure 1 high-speed circuit design _ simplified device interconnect model

Figure 2 is based on the model of the data write timing diagram. In the figure, T0 indicates the delay of the clock from the internal clock generator CLK of the master terminal reaches the clock input of the trigger Q1; T1 indicates the delay of the data when the trigger Q1 receives the clock to the Q1 output; T2 indicates the main control The clock from the internal clock generator CLK to the external clock output pin of the master; T3 indicates the delay of the data output from the internal trigger Q1 to the external data output pin of the master. In general, the semiconductor manufacturer does not give these parameters of T0-T3, usually giving a parameter to reflect the final equivalent effect of these parameters, that is, when the data on the external data pin of the master is compared with the external clock pin The delay of the clock signal appears here as Tco.
High - speed circuit design _ data write timing diagram
Figure 2 high-speed circuit design _ data write timing diagram

Timing analysis of the most concerned about the parameters of the signal to reach the receiving end of the final set-up time and hold time is consistent with the device requirements. Here will be set up time and hold time are recorded as Tsetup and Thold. Tflt-clk and Tflt-data represent the flight time of the clock signal and the data signal, that is, their delay on the corresponding trace. Tjitter-clk and Tjitter-data represent the jitter time on the clock signal and the data signal, respectively.

The settling time and hold time of the device reflect the timing of the timing and the associated target logic timing relationship within the device by describing the timing relationship on the clock pins and data pins outside the device. Signal from the device pin to the internal target logic there is a certain delay, while the internal logic needs to establish and maintain the final time, integrated devices within these needs, and ultimately get the device external timing requirements.

In the analysis of the relationship between the clock signal and the data signal in Figure 2, it can be found that the edge of the device can not be used for data sampling at the receiving end if the clock and data trace between devices are equal due to the presence of Tco The In order to properly sample the data at the receiving end, it is necessary to adjust the relationship between the clock and the data trace. There are two methods. First, the clock traces are longer than the data traces, making the data shorter than the clock. At this point, the receiver can still use the data generated by the clock along the sampling data; Second, the data traces longer than the clock, making the data flight time longer than the clock. At this point, you can use the next rising edge of the generated data clock to sample the data.

In the actual project, the designer generally uses the second method and wants to keep a certain margin for the establishment and maintenance of the digital system, so we can draw the following formula, that is, the establishment of time formula:

(Tset) min + (Tco) max + (Tflt-data - Tflt-clk) max + Tjitter-clk + Tjitter-data <T (1)
And hold time formula:

(Tco) min + (Tflt-data - Tflt-clk) min - Tjitter-clk- ​​Tjitter-data> (Thold) min (2)

Obviously, Tco, Tflt-data, Tflt-clk, Tco is the inherent parameters of the device, Tflt-data and Tflt-clk depends on the corresponding PCB trace length and alignment layer. If the difference between Tflt-data and Tflt-clk is too small, the data retention time is insufficient; if it is too large, the build time is insufficient. Therefore, the difference between the Tflt-data and the Tflt-clk is limited by the upper and lower limits.
High - speed circuit design _ data read timing diagram
Figure 3 high-speed circuit design _ data read timing diagram

Figure 3 is based on the model of the data read timing diagram. The meaning of the parameters in the figure is the same as before. It should be noted that: in the read relationship, the clock first need to pass from the host to the slave, from the end of the data sent back to the host side, the data can be sampled by the host side. Therefore, the formula for establishing and maintaining time is as follows:
(Tset) min + (Tco) max + (Tflt-data) max + (Tflt-clk) min + Tjitter-clk + Tjitter-data <T (3)

(Tflt-clk) max - Tjitter-clk-Tjitter-data (4) & lt; / RTI & gt;

In Tco, Tflt-data, Tflt-clk, To is the intrinsic parameter of the device. Tflt-data and Tflt-clk depend on the corresponding PCB trace length and trace layer. If the sum of Tflt-data and Tflt-clk is too small, the data retention time is insufficient; if it is too large, the build time is insufficient. Thus, the sum of Tflt-data and Tflt-clk is limited by the upper and lower limits.

Need to add that the analysis of the aforementioned formula implies a result that the default device output hold time and output delay are equal. In practice, different semiconductor devices have different situations, even if the same semiconductor device is not necessarily identical in output data at a time. This is the beginning of this article has repeatedly stressed that the timing analysis of the formula is not a panacea, although most of the circumstances are applicable, given the diversity of the real world, specific problems must be specific analysis.

There is also a question: whether the data can be sampled using the next rising edge of the data clock edge, or the edge of the data. Figure 4 shows the 1 # clock edge of the data sent by the 3 # clock edge sampling example, in the foregoing, 1 # clock along the data sent by the # 2 clock edge sampling. Here. In order to have a better setup and hold time at the receiving end, it can be seen that the flight time of the data is preferably greater than one clock cycle. Assuming that the clock cycle is 40ns, the surface is traced and the sheet is FR-4, the minimum length of the data line is 635CM. Even if the clock cycle is 8ns, the minimum length of the data line should be 127CM. This is obviously not what we want. Therefore, the actual use of the data generated by the clock edge of the rising edge to sample the data.
High-speed circuit design _ use data to generate subsequent edge sampling data
Figure 4 High-speed circuit design _ Use data to generate subsequent edge sampling data