With the development of high-speed and high-density circuit design trends, QFN package has a pitch of 0.5mm pitch or even smaller pitch applications. The crosstalk problem in the PCB traversing region introduced by the device with small pitch QFN is also becoming more and more prominent as the transmission rate increases. For 8Gbps and above high-speed applications should pay attention to avoid such problems, high-speed digital transmission link to provide more margin. In this paper, the method of suppressing the crosstalk introduced by small pitch QFN package is simulated and analyzed, which provides a reference for this design.

First, the problem analysis
In PCB designs, QFN-packaged devices typically use microstrip lines to fan the TOP or BOTTOM layers. For small-pitch QFN packages, the distance between the microstrip lines and the length of the parallel traces need to be noted in the fan-out area. Figure 1 is a 0.5 pitch QFN package size map.
0.5 pitch QFN package dimensions
Figure 2 is a typical 1.6mm thick 6-layer PCB design using a 0.5mm pitch QFN package:
QFN package PCB design TOP layer alignment
Differential line line width / line distance: 8/10, the distance from the reference layer 7mil, FR4 for the plate.
PCB differential traces spacing and stacking
From the above design we can see that in the fan-out area difference between the interval and the difference between the line spacing, will make the difference between the pairs of crosstalk increases.
Differential mode port definition and crosstalk simulation results
Figure 4 is the design of the differential mode of the near-end crosstalk and far-end crosstalk simulation results, the figure D1 ~ D6 is the differential port.

From the simulation results, it can be seen that even in the case of parallel traces, the differential port D1 is more than -40dB at 5GHz at 5GHz and -32dB at 10GHz, and the far-end crosstalk reaches -40dB at 15GHz For applications such as 10Gbps and above, this is required

Of the crosstalk to optimize the crosstalk control to -40dB below.

Second, the optimization program analysis
For PCB designs, the more straightforward optimization method is to use tightly coupled differential traces to increase the traces between the differential pairs and to reduce the parallel alignment distance between the differential pairs.

Figure 5 is an example of crosstalk optimization using tightly coupled differential lines for the above design:
Tightly coupled differential wiring diagram
Figure 6 is the design of the differential mode of the near-end crosstalk and far-end crosstalk simulation results:
Tightly coupled checkpoint definition and crosstalk simulation results
From the optimized simulation results, it can be seen that the use of tight coupling and increasing the spacing between differential pairs can reduce the near-end crosstalk between differential pairs in the frequency range of 0 ~ 20G by 4.8 ~ 6.95dB. ~ 20G frequency range reduced by about 1.7 ~ 5.9dB.
Near - end / far - end crosstalk optimization statistics
In addition to pulling the gap between the differential pairs at the time of wiring and reducing the parallel distance, we can also adjust the distance between the differential line and the reference plane to suppress crosstalk. The closer to the reference layer, the more favorable to suppress crosstalk. On the basis of the tight coupling route, we adjust the distance between the TOP layer and its reference layer from 7 mils to 4 mils.
Laminated adjustment diagram
According to the above optimization simulation, the simulation results are as follows:
Crosstalk simulation results after stacking
It is worth noting that when we adjust the distance between the trace and the reference plane, the impedance of the differential line also changes, the need to adjust the differential trace to meet the target impedance requirements. The chip's SMT pad will also become lower after the reference plane distance becomes smaller, and the SMT pad needs to be pinned on the reference plane of the SMT pad to optimize the impedance of the SMT pad. The size of the specific hollowed out need to be based on the simulation of the stack to determine.
Stability diagram of QFN pad after stacking adjustment
It can be seen from the simulation results that adjusting the distance between the traces and the reference plane, using the tight coupling and increasing the spacing between the differential pairs can reduce the near-end crosstalk between the differential pairs in the frequency range of 0 ~ 20G by 8.8 ~ 12.3 DB. The far - end crosstalk is reduced by 2.8 ~ 9.3dB in the range of 0 ~ 20G.
Near - end / far - end crosstalk optimization statistics

Third, the conclusion
By simulation, we can reduce the near-end differential crosstalk caused by small-pitch QFN on the PCB by 8 ~ 12dB, reduce the remote crosstalk by 3 ~ 9dB, and provide more margin for the high-speed data transmission channel. In this paper, the crosstalk suppression method can be used in the development of PCB routing rules and stacking considerations, in the early PCB design to avoid the small pitch QFN package to bring the risk of crosstalk.