4, non-wear hole technology
 
Non-penetrating holes contain blind holes and buried holes. In the non-penetration hole technology, the application of blind hole and buried hole can greatly reduce the size and quality of PCB, reduce the number of layers, improve the electromagnetic compatibility, increase the characteristics of electronic products, reduce costs, but also make the design work more Simple and quick.
 
In traditional PCB design and processing, through-hole will bring many problems. First of all they occupy a large number of effective space, followed by a large number of holes through a multi-layer PCB layer also caused a huge obstacle, these holes accounted for the necessary space to walk, they are dense through the power and ground Line layer of the surface, but also damage the power line layer of the impedance characteristics, so that power ground layer failure. And the conventional mechanical drilling will be 20 times the amount of non-penetration hole technology.
 
In the PCB design, although the size of the pad and vias has been gradually reduced, if the thickness of the slab does not decrease proportionally, the aspect ratio of the through-hole will be increased and the aspect ratio of the through-hole will be reduced. With the advanced laser drilling technology, the plasma dry etching technology is mature, the application of non-penetrating small blind hole and small buried hole as possible, if these non-perforated hole hole diameter of 0.3mm, the parasitic parameters are The original conventional hole about 1/10, to improve the reliability of the PCB. Due to the use of non-penetration hole technology, making the PCB on the large vias will be very small, so you can provide more space for the alignment.
 
The remaining space can be used for large area shielded applications to improve EMI / RFI performance. While more free space can also be used for the inner part of the device and the key line of cable shielding, it has the best electrical performance. The use of non-penetrating holes makes it easier to fan out the device pins, making high-density pin devices (such as BGA package devices) easy to wire, shorten the length of the connection to meet the high-speed circuit timing requirements.
 
5, the common PCB in the hole selection
 
In the ordinary PCB design, the parasitic capacitance and parasitic inductance of the vias have little effect on the PCB design. For the 1-4 layer PCB design, the general selection is 0.36mm / 0.61mm / 1.02mm, (drilling / pad / POWER isolation (Such as power lines, ground, clock lines, etc.) can be used 0.41mm / 0.81mm / 1.32mm vias, but also according to the actual selection of the remaining size of the hole The
 
6, high-speed PCB in the hole design
 
Through the above analysis of the parasitic characteristics of the hole, we can see that in the high-speed PCB design, the seemingly simple vias often also give the circuit design a great negative effect. In order to reduce the parasitic effects of the hole caused by the adverse effects in the design can be done as far as possible:
 
(1) Select a reasonable via size. For multi-layer general density PCB design, the use of 0.25mm / 0.51mm / 0.91mm (drilling / pad / POWER isolation area) better than the hole; for some high-density PCB can also use 0.20mm / 0.46 Mm / 0.86mm vias, you can also try non-wear holes; for power or ground vias can be considered to use a larger size to reduce the impedance;
 
(2) POWER isolation area as possible, consider the PCB on the hole density, generally D1 = D2 +0.41 mm
 
(3) PCB signal traces as far as possible without layer, that is to say to minimize the hole;
 
(4) the use of thinner PCBs can help reduce the two parasitic parameters of the vias;
 
(5) the power and ground pins to do the nearest hole, between the vias and pins between the lead as short as possible, because they will lead to increased inductance. While the power and ground lead should be as thick as possible to reduce the impedance;
 
(6) Place some ground vias near the vias of the signal transfer layer to provide a short distance loop for the signal. Of course, the design needs specific analysis of specific issues. From the cost and signal quality of both considerations, in the high-speed PCB design, the designer always want the smaller the better the hole, so the board can leave more wiring space, in addition, the smaller the hole, its own Parasitic capacitance is also smaller, more suitable for high-speed circuit. In high-density PCB designs, the use of non-penetrating vias and through-hole sizes reduces the cost of the increase, and the size of the vias can not be reduced indefinitely, it is PCB manufacturers drilling and plating process Technical limitations, in the high-speed PCB through-hole design should be balanced to consider.