4, PCB layout: lead length

Maxim's ISM-RF product data is often recommended to use the shortest possible high-frequency input and output leads, thus minimizing losses and radiation. On the other hand, this loss is usually caused by non-ideal parasitic parameters, so parasitic inductance and capacitance will affect the PCB circuit layout, using the shortest lead to help reduce the parasitic parameters. Typically, 10mil wide, 0.0625in from the formation of the PCB lead, if the use of FR4 circuit board, then produce about 19nH / in the inductance and about 1pF / in the distribution of capacitance. For a 20nH inductor, 3pF capacitor LAN / mixer circuit, circuit, component layout is very compact, the effective component value will have a great impact.

The IPC-D-317A in the "Institute for Printed Circuits" provides an industry standard equation for estimating the various impedance parameters of the microstrip PCB. The document was replaced by IPC-2251 in 2003, which provides a more accurate calculation for various PCB leads. Online calculators are available through a variety of channels, most of which are based on the equations provided by IPC-2251. The University of Missouri's Electromagnetic Compatibility Laboratory provides a very practical PCB lead impedance calculation method.

The accepted standard for calculating the microstrip line impedance is:
PCB layout
Where εr is the dielectric constant of the dielectric, h is the height of the lead from the formation, w is the lead width, and t is the lead thickness (Fig. 7). When the w / h is between 0.1 and 2.0 and the εr is between 1 and 15, the formula is fairly accurate.
PCB layout _PCB cross section
Figure 7: PCB layout _ The picture shows the PCB cross-section, indicating the structure used to calculate the microstrip line impedance

To evaluate the effect of lead length, it is more practical to determine the detonation effect of the lead parasitic parameters for the ideal circuit. In this case, we discuss stray capacitance and inductance. The standard capacitance for the microstrip line is:
PCB layout
Similarly, the characteristic inductance can be calculated from the equation PCB layout using the above equation:
PCB layout
For example, assume that the PCB thickness is 0.0625 in (h = 62.5 mil), 1 ounce copper wire (t = 1.35 mil), width 0.01in (w = 10 mil), using FR-4 circuit board. Note that the εr of FR-4 is typically 4.35 Farads / m (F / m), but ranges from 4.0F / m to 4.7F / m. The eigenvalues ​​calculated in this example are Z0 = 134Ω, C0 = 1.04pF / in, L0 = 18.7nH / in.

For ISM-RF designs, lead lengths of 12.7 mm (0.5 in) on the board can produce parasitic parameters of approximately 0.5 pF and 9.3 nH (Figure 8). The effect of this grade of parasitic parameters on the receiver resonant tank (changes in LC product) may result in a change of 315 MHz ± 2% or 433.92 MHz ± 3.5%. Due to the additional capacitance and inductance generated by the parasitic effects of the leads, the peak of the 315 MHz oscillation frequency reaches 312.17 MHz and the peak of the 433.92 MHz oscillation frequency reaches 426.61 MHz.
PCB layout _ parasitic effects
Figure 8: A compact PCB layout, the parasitic effect will have an impact on the circuit

Another example is the resonant tank path of Maxim's superheterodyne receiver (MAX7042). The recommended components are 1.2pF and 30nH at 315MHz and 0pF and 16nH at 433.92MHz. Calculate the resonant circuit using the equation Oscillation frequency:
PCB layout
The evaluation board resonant circuit should include the parasitic effect of the package and layout. When calculating the 315MHz resonant frequency, the parasitic parameters are 7.3pF and 7.5pF, respectively. Note that the LC product behaves as a lumped capacitor.

Therefore, the PCB layout must follow the following principles:

Keep the lead length as short as possible.

The critical circuit is placed as close as possible to the device.

According to the actual layout parasitic effect of the key components to compensate.

5, PCB layout: ground and fill processing

Grounding is the power supply layer defines a common reference voltage, through the low resistance path for all components of the system power supply. In accordance with this way to balance all the electric field, resulting in a good shielding mechanism.

The DC current always tends to flow along the low resistance path. Similarly, high-frequency current is also preferred to flow through the lowest resistance path. So, for the standard PCB microstrip lines above the formation, the return current is trying to flow into the ground region just below the lead. According to the lead coupling described above, the cut ground region introduces various noise, which in turn increases crosstalk by magnetic field coupling or converging current (Fig. 9).
PCB layout _ ground
Figure 9: PCB layout _ Keep the formation as complete as possible, otherwise the return current will cause crosstalk

Filling is also known as a protective line, which is usually used in circuits where it is difficult to lay a continuous grounded area or require a shielded sensitive circuit design (Figure 10). The shielding effect is increased by placing a ground via (ie, a via array) at both ends of the lead, or along the line. Please do not mix the protection lines with the leads designed to provide the return current path. This layout introduces crosstalk.
PCB layout _ fill
Figure 10: PCB layout _RF system design to avoid the copper wire floating, especially the need to lay the case of copper

The copper area is not grounded (floating) or only at one end of the ground, it will restrict its effectiveness. In some cases, it creates parasitic capacitance, changes the impedance of the surrounding wiring, or creates a "potential" path between the circuits, resulting in adverse effects. In short, if a copper (non-circuit signal trace) is laid on the board to ensure a consistent plating thickness. Copper cladding areas should be avoided floating because they affect the circuit design.

Finally, make sure to consider the impact of any ground area near the antenna. Any monopole antenna will be grounded, traces and vias as part of the system equalization, non-ideal balanced wiring will affect the antenna radiation efficiency and direction (radiation template). Therefore, the ground area should not be placed directly below the unipolar PCB lead antenna.

Therefore, PCB layout should follow the following principles:

Try to provide continuous, low resistance ground area.

Fill the ends of the filling wire and use the via array as far as possible.

Do not place the copper wire around the RF circuit. Do not lay out the copper around the RF circuit.

If the circuit board includes multiple formation, the signal line from one side over the other side, it is best to lay a ground vias.

6, PCB layout: crystal capacitor is too large

The parasitic capacitance causes the operating frequency of the crystal to deviate from the target value. Therefore, the PCB layout must follow some conventional guidelines to reduce the crystal pins, pads, traces, or stray capacitance connected to RF devices.

PCB layout should follow the following principles:

The connection between the crystal and the RF device is as short as possible.

The traces of each other are kept as isolated as possible.

If the parasitic capacitance is too large, remove the grounded area below the crystal.

7, PCB layout: plane alignment inductance

The use of planar traces or PCB spiral inductors is not recommended. Typical PCB manufacturing processes have a certain inaccuracies, such as width and spatial tolerances, which have a significant effect on component accuracy. As a result, most controlled and high Q inductors are wound. Second, you can choose multi-layer ceramic inductors, multi-layer chip capacitor manufacturers also provide this product. Nevertheless, some designers still have a helical inductance in the case of a last resort. The standard formula for calculating the planar spiral inductor is usually given by the Wheeler formula:
PCB layout
Where a is the average radius of the coil in inches, n is the number of turns, and c is the width of the coil core (rOUTER - rINNER) in inches. When the coil c> 0.2a.