Numerous application cases for industrial, scientific and medical radio frequency (ISM-RF) products show that various PCB layout defects for these products are prone to occur. People often find the same IC installed on two different circuit boards, the performance of the performance indicators will be significantly different. Working conditions, harmonic radiation, anti-jamming capability, as well as start-up time and many other factors change, can explain the PCB layout in a successful design of the importance.

This paper lists a variety of design failures, discusses the causes of each failure leading to circuit failures, and gives advice on how to avoid these design flaws. In this paper, FR-4 dielectric, thickness of 0.0625in double-layer PCB, for example, the bottom of the circuit board ground. Operating frequency between 315MHz and 915MHz between the different bands, Tx and Rx power between -120dBm to +13 dBm between. Table 1 lists some of the possible PCB layout problems, causes and impact.
PCB layout _ typical PCB layout problems and effects
Table 1: PCB Layout _ Typical PCB Layout Issues and Effects

Most PCB layout problems stem from a few common causes:

PCB layout: inductance direction

PCB layout: lead coupling

PCB layout: ground via

PCB layout: lead length

PCB layout: ground and fill processing

PCB layout: crystal capacitor is too large

PCB layout: Plane alignment inductance

Then we will discuss the above points one by one.

1, PCB layout: inductance direction

When two inductors (or even two PCB traces) are close to each other, there will be mutual inductance. The magnetic field generated by the current in the first circuit will energize the current in the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary windings of the transformer.

When two currents interact through the magnetic field, the resulting voltage is determined by the mutual inductance LM:
PCB layout
Where YB is the error voltage injected into circuit B and IA is the current acting on circuit A. LM is very sensitive to circuit spacing, inductive loop area (ie, magnetic flux) and loop direction. Thus, the best balance between the compact circuit layout and the reduced coupling is the proper arrangement of all the inductive directions.
PCB layout _ magnetic field lines
Figure 1: PCB layout _ by the magnetic field lines can be seen in the direction of mutual inductance and inductance

The direction of circuit B is adjusted so that its current loop is parallel to the magnetic field lines of circuit A. For this purpose, try to make the inductance perpendicular to each other. Refer to the low power FSK superheterodyne receiver evaluation (EV) board (MAX7042EVKIT) circuit layout (Figure 2). The three inductors (L3, L1 and L2) on the circuit board are very close, and their directions are arranged at 0 °, 45 ° and 90 °, helping to reduce mutual inductance.
PCB layout _ component arrangement direction
Figure 2: Two different PCB layouts

In the above figure, the layout of one of the layout elements is unreasonable (L1 and L3), and the arrangement of the other PCB layout is more appropriate.

Therefore, PCB layout should follow the following principles:

The inductance spacing should be as far away as possible.

The inductor is oriented at right angles to minimize crosstalk between inductors.

2, PCB layout: lead coupling

As the direction of the inductor arrangement affects the magnetic field coupling, if the leads are too close to each other, the coupling will also be affected. This layout problem also produces so-called mutual inductance. RF circuit is one of the most concerned about the problem of system-sensitive components of the alignment, such as input matching network, the receiver of the resonant tank, the transmitter antenna matching network.

The return current path should be as close as possible to the main current path to minimize the radiation field. This layout helps to reduce the current loop area. The ideal low resistance path for the return current is typically the ground region below the lead - the area where the loop area is effectively limited to the thickness of the dielectric multiplied by the lead length. However, if the grounded area is divided, the loop area is increased (Figure 3). For leads passing through the divided area, the return current will be forced through the high resistance path, greatly increasing the current loop area. This layout also makes circuit leads more susceptible to mutual influence.
PCB layout _ lead coupling
Figure 3: PCB layout _ complete large area grounding helps improve system performance

For a real inductance, the direction of the lead on the magnetic field coupling is also great. If the leads of the sensitive circuit must be close to each other, it is preferable to arrange the lead wires vertically to reduce the coupling (Fig. 4). If the vertical arrangement can not be done, consider using a protective cable. For the design of the protection line, refer to the following ground and fill processing section.
PCB layout _ magnetic field coupling
Figure 4: PCB layout _ possible magnetic field coupling.

Therefore, PCB layout should follow the following principles:

Lead should be fully grounded below the lead.

Sensitive leads should be arranged vertically.

If the leads must be arranged in parallel, make sure that the spacing is sufficient or the protective line is used.

3, PCB layout: ground through the hole

The main problem with RF circuit layout is usually that the characteristic impedance of the circuit is not ideal, including circuit elements and their interconnections. The lead copper layer is thinner, which is equivalent to the inductor line and forms a distributed capacitance with the adjacent leads. When the leads pass through the vias, they also exhibit inductance and capacitance characteristics.

The via capacitance is mainly due to the capacitance between the copper cladding on the vias side and the cladding copper, which is separated by a relatively small ring. Another effect comes from the metal hole in the cylinder itself. The effect of parasitic capacitance is generally small, usually only cause high-speed digital signal edge deterioration (this article omitted).

The biggest effect of the vias is the parasitic inductance caused by the corresponding interconnection. Because most metal vias are the same size as the lumped components in RF PCB designs, the effects of circuit vias can be estimated using a simple formula (Figure 5):
PCB layout
Where, LVIA for the hole of the lumped inductance; h for the hole height, in inches; d for the diameter of the hole, in inches.
PCB layout _PCB cross section
Figure 5: PCB layout _PCB cross-section is used to estimate the parasitic effects of the via structure

Parasitic inductors often have a great impact on the connection of the bypass capacitors. The ideal bypass capacitor provides a high frequency short circuit between the power plane and the formation, but the non-ideal vias will affect the low sensing path between the formation and the power plane. A typical PCB vias (d = 10 mil, h = 62.5 mil) are approximately equivalent to a 1.34nH inductor. Given a specific operating frequency of an ISM-RF product, vias can adversely affect sensitive circuits such as resonant trenches, filters, and matching networks.

If the sensitive circuit shares vias, such as the two arms of a π-type network, other problems arise. For example, placing an ideal vias equivalent to a lumped inductance, the equivalent schematic is very different from the original circuit design (Figure 6). And the common current path of the crosstalk, resulting in mutual inductance increases, increase crosstalk and feedthrough.
PCB layout _ signal path
Figure 6: PCB layout _ ideal architecture and non-ideal architecture, the circuit there is a potential "signal path"

Therefore, PCB layout in the layout of the circuit need to follow the following principles:

Ensure that the inductor in the sensitive area is modeled.

The filter or matching network uses a separate vias.

Note: Thin PCB copper will reduce the effect of vias parasitic inductance.