The formation of peak current:
When the digital circuit outputs a high level, the current Ioh pulled out from the power supply and the current Iol at the low level output are generally different, ie, Iol> Ioh. The following figure shows the formation of the peak current as an example:
Output voltage As shown in the right figure (a), the theoretical supply current waveform as shown in Figure (b), and the actual power supply current insurance as shown in Figure (c). It can be seen from Fig. (C) that the supply current has a short and large spike when the output transitions from high to high. The waveform of the peak supply current varies depending on the type of device used and the capacitive load connected to the output.

The main cause of spikes is:
The output stage of the T3, T4 tube is short in the design. In the NAND gate from the output low to high level of the process, the input voltage of the negative transition in the T2 and T3 of the base circuit to produce a large reverse drive current, the saturation depth of T3 designed to be more than T2 The large and reverse drive current will cause T2 to first release from saturation. T2 cut off, the collector potential rise, so T4 conduction. But at this time T3 is not out of saturation, so in a very short design T3 and T4 will be the same time conduction, resulting in a large ic4, so that the formation of peak current supply current. The figure R4 is designed to limit this spike current.
The R4 in the low-power TTL gate is larger, so its peak current is small. When the input voltage from low to high, the non-gate output level from high to low, then T3, T4 may also turn on. But when T3 starts to turn on, T4 is in the magnified state, the two tube set-shot voltage is large, so the generated peak current is small, the impact on the power supply current is relatively small.
Another reason for generating a spike current is the effect of the load capacitance. The non-gate output actually has a load capacitance CL. When the output of the gate changes from low to high, the supply voltage is charged by T4 to capacitor CL, thus forming a peak current.
When the output of the NAND gate is switched from high to low, the capacitor CL is discharged through T3. At this point the discharge current does not pass the power supply, so the CL discharge current has no effect on the supply current.

The method of suppressing the peak current:
1, in the circuit board wiring to take measures to make the signal line stray capacitance to a minimum;
2, another method is to try to reduce the internal resistance of the power supply, so that the peak current will not cause excessive power supply voltage fluctuations;
3, the usual practice is to use decoupling capacitors to filter, usually in the circuit board power supply entrance
A 1uF ~ 10uF decoupling capacitor, filter out low-frequency noise; in the circuit board of each active device between the power supply and place a 0.01uF ~ 0.1uF decoupling capacitor (high-frequency filter capacitor) for Filter out high frequency noise. The purpose of filtering is to filter out the AC interference superimposed on the power supply, but not the larger the capacitor capacity, because the actual capacitance is not the ideal capacitor and does not have all the features of the ideal capacitor.
The decoupling capacitor can be selected according to C = 1 / F, where F is the circuit frequency, that is, 10MHz take 0.1uF, 100MHz take 0.01uF. Generally take 0.1 ~ 0.01uF can be.
Placed in the active device near the role of high-frequency filter capacitor has two, one is to filter out along the power transmission over the high-frequency interference, and the second is to complement the high-speed operation of the device required peak current. So the location of the capacitor is to be considered.
The actual capacitance due to the presence of parasitic parameters can be equivalent to the series resistance and inductance in the capacitor, which is called equivalent series resistance (ESR) and equivalent series inductance (ESL). In this way, the actual capacitance is a series resonant circuit, the resonant frequency is:
The same time as
        PCB placement and how to install and install decoupling capacitors
The actual capacitance is capacitive at frequencies below Fr, and at a frequency higher than Fr, the capacitance is more like a band-stop filter.
10uF electrolytic capacitor due to its larger ESL, Fr less than 1MHz, for 50Hz such low-frequency noise has a better filtering effect on the hundreds of megabytes of high-frequency switching noise is no effect.
The ESR and ESL of the capacitor are determined by the structure of the capacitor and the medium used, not the capacitance. By using a larger capacity capacitor can not improve the ability to suppress high-frequency interference, the same type of capacitance, at a frequency lower than Fr, the large capacity than the small-capacity impedance is small, but if the frequency is higher than Fr, ESL determines The impedance of the two will not be any difference.
The use of excessive capacity on the circuit board for filtering high-frequency interference and no help, especially when using high-frequency switching power supply. Another problem is that large capacity capacitors, increased power and hot-swappable circuit board when the impact of power, easy to cause such as power supply voltage drop, circuit board connector ignition, board voltage rise and other issues.

        PCB layout when the decoupling capacitor placed
For the installation of capacitors, the first thing to mention is the installation distance. Capacitance with the smallest capacitance has the highest resonant frequency and the decoupling radius is minimal, so it is placed closest to the chip. The value of a little larger can be a little far away, the outermost placed the largest value. However, all the capacitors that are decoupled to the chip are as close as possible to the chip.
Here is an example of an placement. The capacitance level in this example roughly follows the 10-fold level relationship.

        How to Install Decoupling Capacitors In PCB Layout
Another point to note, in the placement, the best evenly distributed in the chip around, for each level of value should be so. Usually the chip in the design of the time to take into account the power and ground pin arrangement, are generally evenly distributed in the chip on the four sides. Therefore, the voltage disturbance exists around the chip, decoupling must also be the entire chip where the region evenly decoupling. If the above figure in the 680pF capacitor are placed on the upper part of the chip, due to the existence of decoupling radius problem, then the lower part of the chip voltage disturbance can not be a good decoupling.

Capacitor installation
When installing the capacitor, pull out a short lead from the pad, and then through the hole and power plane connection, the ground is the same. The current loop through the capacitor is: power plane - "through-hole" - lead - "pad -" capacitor - "pad -" lead - "via -" ground plane, the following figure shows the current Of the return path.

PCB placement and how to install and install decoupling capacitors
The first way to draw a long lead from the pad and then connect the vias, which will introduce a large parasitic inductance, be sure to avoid doing this, which is the worst way to install.
The second method closes the pad at the two ends of the pad, much smaller than the first method, and the parasitic inductance is smaller and acceptable.
The third hole in the side of the pad, further reducing the loop area, parasitic inductance is smaller than the second, is a better way.
The fourth on both sides of the pad are perforated, and compared to the third method, the equivalent of each end of the capacitor through the parallel through the hole into the power plane and ground plane, smaller than the third parasitic inductance, as long as Space allows, try to use this method.
The last method to punch directly on the pad, parasitic inductance is minimal, but the welding is likely to be a problem, whether to use to see the processing capacity and manner.
It is recommended to use the third and fourth methods.

Need to emphasize that some engineers in order to save space, and sometimes allow multiple capacitors to use public vias, in any case do not do so. It is best to try to optimize the design of the capacitor combination to reduce the number of capacitors.
As the width of the printed circuit, the smaller the inductance, from the pad to the hole of the lead wire as wide as possible, if possible, as much as the same width and pad. So that even 0402 package capacitor, you can also use the 20mil wide lead wire. The lead-out and vias are installed as shown in Figure 4, taking note of the various sizes in the figure.