We often find that some of the rules or principles of their own tend to have some mistakes. Electronic engineers in the circuit design will have such an example. The following is an engineer summary of the eight errors.

Misunderstanding 1: This board of PCB design requirements are not high, with a little fine line, automatic cloth

Comments: automatic wiring is bound to take up a larger PCB area, while producing more than a few times the manual wiring through the hole, in a large batch of products, PCB manufacturers to consider the factors in addition to factors in addition to business factors, is the line width and The number of holes, which were affected by the PCB yield and the number of drill bit consumption, saving the cost of the supplier, also gave the price to find a reason.

Misunderstanding 2: These bus signals are pulled with resistance, feel more rest assured

Comments: the signal needs to pull down a lot of reasons, but not all have to pull. Pull-down resistor pull a simple input signal, the current will be several tens of microamps below, but pull a driven signal, the current will reach the mA level, the current system is often the address data of 32, there may be 244/245 isolated bus and other signals, are pulled up, then a few watts of power consumption on the resistance of the.

Misunderstanding 3: CPU and FPGA of these unused I / O mouth how to deal with it? Let it empty it, later say

Comments: do not have the I / O port if floating, then a little bit of interference by the outside may become a repeated oscillation of the input signal, and MOS device power depends on the number of flip the door circuit. If it pulls it up, then each pin will have micro-level current, so the best way is set to output (of course, can not be connected to other outside the drive signal)

Misunderstanding 4: This FPGA left so many doors can not finish, you can play

Comments: FGPA power consumption and the number of flip-flops used and the number of flip is proportional to the same type of FPGA in different circuits at different times the power consumption may be a difference of 100 times. Minimizing the number of flip flops at high speed is the fundamental way to reduce FPGA power consumption.

Mistakes 5: these small chip power consumption is very low, do not consider

Comments: For the internal less complex chip power is difficult to determine, it is mainly determined by the current on the pin, an ABT16244, no load, then the power consumption of less than 1 mA, but its indicators are each foot Can drive 60 mA load (such as matching tens of ohms resistance), that is, the maximum power consumption of up to 60 * 16 = 960mA, of course, only the power supply current is so big, the heat fell on the load.

Misunderstanding 6: memory has so much control signal, I only need this board with OE and WE signal on it, chip election to ground it, so read the data when the operation came much faster

Comments: Most of the memory power consumption in the chip selection is valid (regardless of OE and WE how) will be more than 100 times more than the film selection is invalid, so should use CS as much as possible to control the chip, and meet other requirements to do so May shorten the width of the chip select pulse.

Misunderstanding seven: how these signals have overshoot ah? As long as the match is good, you can eliminate the

Comments: In addition to a few specific signals (such as 100BASE-T, CML), are overshoot, as long as not very large, do not necessarily need to match, even if the match is not to match the best. Like the TTL output impedance of less than 50 ohms, and some even 20 ohms, if also with such a large matching resistance, then the current is very large, power consumption is unacceptable, the other signal amplitude will be small can not be used, Besides the general signal output high and low output impedance when the output is not the same, there is no way to achieve perfect match. So the TTL, LVDS, 422 and other signal matching as long as the overshoot can be accepted.

Misunderstanding 8: reduce power consumption is the hardware staff, and software does not matter

Comments: the hardware is just take a stage, singing is the software, the bus almost every chip access, each signal flipped almost by the software control, if the software can reduce the number of external access (more use of register variables, The use of internal CACHE, etc.), timely response to interrupt (interrupt is often active low and with a pull-up resistor) and other specific measures against the specific board will reduce the power to make a great contribution.