Based on recent trends, improving efficiency becomes a key goal, it is not worth the trade-offs of slow switching devices to get better EMI. Super junctions can improve efficiency in applications where flat MOSFETs are difficult to perform. Compared with traditional planar MOSFET technology, the super-junction MOSFET can significantly reduce the on-resistance and parasitic capacitance. The significant reduction in on-resistance and the reduction in parasitic capacitance contribute to the increased efficiency, but also the rapid switching of voltage (dv / dt) and current (di / dt), resulting in high frequency noise and radiated EMI.

To drive fast switching super-junction MOSFETs, it is important to understand the effects of encapsulation and PCB layout parasitic effects on switch performance, as well as PCB layout adjustments for using super junctions. Mainly using the breakdown voltage of 500-600V super-junction MOSFET. Among these voltage ratings, the industry standard TO-220, TO-247, TO-3P and TO-263 are the most widely used packages. The impact of the package on performance is limited because the internal gate and source binding lines are fixed in length. Only the length of the pin can be changed to reduce the source inductance of the package. As shown in Figure 1 (a), the typical lead inductance of 10nH does not look much, but the di / dt of these MOSFETs can easily reach 500A / μs! Assuming di / dt is 500A / μs, the voltage on the 10nH lead inductance is VIND = 5V; and the 10nH lead inductance turns off di / dt to 1,000 A / μs, resulting in VIND = 10V. Most applications and designs do not take into account this additional inductance will produce voltage, but this can not be ignored. The above simple calculation shows that the total source inductance of the package, that is, the binding line and the pin inductance must be reduced to an acceptable value. Another source of noise is the layout parasitic effect. There are two visible layout parasitic effects: parasitic inductance and parasitic capacitance. 1cm trace inductance for the 6-10nH, by adding a layer at the top of the PCB and add the bottom of the PCB layer of GND, can reduce this inductance. The other type is parasitic capacitance. Figure 1 (b) shows the principle of capacitive parasitic effects in the layout. The parasitic capacitance is caused by a connection between two adjacent traces or between the traces and the other side of the ground plane. The other capacitor is the capacitance between the device and the ground plane. PCB on both sides of the two parallel lines can increase the capacitance, while also reducing the loop inductance, thereby reducing the electromagnetic noise radiation. Please consider these layout tips when the next design requires a super-junction MOSFET.
Encapsulation and distribution of parasitic elements in the layout
Because the MOSFET is a unipolar device, the parasitic capacitance is the only limiting factor in the switching transient. The charge balance principle reduces the on-resistance of a particular area, and the chip size under the same RDS (ON) is smaller than the standard MOSFET technology. Figure 1 shows the capacitance of a super-junction MOSFET and a standard planar MOSFET. The Coss of the standard MOSFET is moderately linear and the Coss curve of the super-junction MOSFET exhibits a highly non-linear relationship. Because the cell density is high, the Coss initial value of the super-junction MOSFET is higher, but in the super-junction MOSFET, the Coss will drop rapidly in the vicinity of about 50V drain-source voltage, as shown in Fig. These non-linear effects can cause voltage and current oscillations when using super-junction MOSFETs for PFC or DC / DC converters. Figure 3 shows a simplified schematic diagram of a simplified PFC circuit that includes a power MOSFET internal parasitic element and an external oscillator circuit that contains the external coupling capacitance Cgd_ext from the board.
Comparison of Output Capacitance of Planar MOSFET and Super Junction MOSFETs
Figure 2: Comparison of output capacitance of planar MOSFET and super junction MOSFETs

In general, there are multiple oscillating circuits that affect the switching characteristics of the MOSFET, including internal and external oscillator circuits. In the PFC circuit of Fig. 3, L, Co and Dboost are inductors, output capacitors and boost diodes, respectively. Cgs, Cgd_int and Cds are the parasitic capacitances of the power MOSFET. Ld1, Ls1 and Lg1 are the drain, source and gate bonding lines of the power MOSFET and pin inductance. Rg_int and Rg_ext are the internal gate resistance of the power MOSFET and the external gate drive resistance of the circuit. Cgd_ext is the parasitic gate-drain capacitance of the circuit. LD, LS and LG are printed circuit board (PCB) drain, source and gate traces of stray inductance. When the MOSFET is turned on or off, the gate parasitic oscillation occurs through the gate-drain capacitance Cgd and the gate lead inductance Lg1 in the resonant circuit.
A diagram of a PFC circuit containing internal and external parasitic elements of the power MOSFET
Figure 3: Schematic diagram of the PFC circuit with internal and external parasitic elements of the power MOSFET

Under the resonant condition (ωL = 1 / ωC), the oscillating voltage generated in the gate and source voltages is much larger than the driving voltage. The voltage oscillation due to the change in resonance is proportional to the quality factor, Q (= ωL / R = 1 / ωCR). When the MOSFET is turned off, the drain parasitic inductance (LD + Ld1), the gate-drain capacitance Cgd and the gate lead inductance Lg1 network cause the gate oscillation voltage. If the gate resistance (RG-ext. + Rg_int.) Is extremely small, Q becomes larger. In addition, the voltage drop across the LS and the Ls1 source stray inductance oscillates in the gate-source voltage and can be expressed by the expression (1). Parasitic oscillations can cause gate-source breakdown, poor EMI, large switching losses, gate control failure, and possibly even MOSFET failure.
How to optimize the PCB design to maximize the performance of the super-junction MOSFET
Optimizing the circuit design to maximize the performance of the super-junction MOSFET without causing negative effects is very important.