This article describes how changes in the process cause the actual impedance to change, and how to use accurate field solver to predict this phenomenon. Even if there is no process change, other factors will cause the actual impedance is very different. In the design of high-speed circuit boards, automated design tools sometimes can not find this is not very obvious but very important issues. However, as long as the early steps in the design to take some measures to avoid this problem. This technique is called "defensive design".
Number of stacks
A good stacking structure is the best precautionary measure for most signal integrity problems and EMC problems, and it is also most misleading. There are several factors here that work, and a good way to solve a problem may lead to the deterioration of other problems. Many system design suppliers will recommend that the circuit board should have at least one continuous plane to control the characteristic impedance and signal quality, as long as the cost can afford, this is a good suggestion. EMC consultants often recommend placing ground fill or ground layers on the outer layer to control electromagnetic radiation and sensitivity to electromagnetic interference, which is also a good idea under certain conditions.
Capacitance model
Figure 1: Analysis of signal problems in a laminated structure using a capacitance model
However, due to transient current reasons, in some common design using this method may be in trouble. First, let's look at a simple case of the power plane / ground layer: it can be seen as a capacitor. It can be said that the power plane and ground layer are two plates of capacitance. To obtain a larger capacitance, the two plates are required to be closer (distance D) and increase the dielectric constant (ε ▼ r ▼). The larger the capacitance, the lower the impedance, which is what we want because it can suppress noise. Regardless of how the other layers are arranged, the mains and ground layers should be adjacent and in the middle of the stack. If the power supply layer and the ground layer spacing is large, it will cause a large current loop and bring a lot of noise. If an 8-layer board, the power layer on the side and the ground layer on the other side, will lead to the following questions:
1. The largest crosstalk. As the interactive capacitance increases, the crosstalk between the signal layers is greater than the crosstalk of the layers themselves.
2. The largest circulation. The current flows around the power supply layers and is in parallel with the signal, and a large amount of current enters the main power supply layer and is returned through the ground layer. EMC characteristics will deteriorate due to increased circulation.
3. Loss of control of the impedance. The farther the signal from the control layer, the lower the accuracy of the impedance control due to the presence of other conductors around it.
4. As a result of solder short circuit, may increase the cost of the product.
We have to compromise between performance and cost, so how do I arrange digital boards to get the best SI and EMC features?
The distribution of PCB layers is generally symmetrical. No more than two signal layers should be placed adjacent to each other; otherwise, control of SI will be lost to a large extent. It is advisable to place the internal signal layers symmetrically in pairs. Unless some signals need to be connected to the SMT device, we should minimize the signal routing of the outer layer.
Laminated structure
Figure 2: The first step in the excellent design is to design the stack structure correctly
For more layers of the circuit board, we can put this placement method repeated many times. It is also possible to add additional power and ground layers as long as there is no pair of signal layers between the two power planes.
The wiring of the high-speed signal should be arranged in the same pair of signals; unless it is necessary to violate this principle due to the connection of the SMT device. All traces of a signal should have a common return path (ie, the ground layer). There are two ways and methods to determine what kind of two layers can be seen as a pair:
1. Ensure that the return signal at equal distance is exactly equal. This means that signals should be symmetrically routed on both sides of the internal ground layer. The advantage of doing so is easy to control the impedance and circulation; the disadvantage is that there are many vias on the ground layer, and there are some useless layers.
2. Two adjacent signal layers. The advantage is that the vias in the ground layer can be controlled to a minimum (with buried vias); the disadvantage is that the effectiveness of this method for some critical signals is reduced.
With the second method, the ground connection of the component drive and the received signal is preferably directly connected to the level adjacent to the signal wiring layer. As a simple routing principle, the surface wiring width should be less than one-third of the rise time of the driver in milliseconds (for example, high-speed TTL wiring width is 1 inch).
If there is more power supply, between the power supply lines must be laid between the ground layer so that they separated. Can not form a capacitor, so as not to cause the AC connection between the power supply.
The above measures are to reduce circulation and crosstalk, and enhance the impedance control. The ground layer also forms an effective EMC "shield box". Considering the influence of the characteristic impedance, the unused surface area can be made into the ground layer.
Characteristic impedance
A good stack structure can be effectively controlled on the impedance, the alignment can be easy to understand and predictable transmission line structure. The on-site solution works well with such problems, and as long as the number of variables is minimized, you can get fairly accurate results.
However, when more than three signals are stacked together, the situation is not necessarily the case, the reason is very subtle. The target impedance depends on the device's process technology. High-speed CMOS technology can generally reach about 70Ω; high-speed TTL devices can generally reach about 80Ω to 100Ω. Because the impedance value usually has a great impact on the noise margin and the signal switching, the impedance selection needs to be very careful; the product specification should give guidance.
The initial results of the on-site solution tool may encounter two problems. The first is that the field of view is limited, and the field resolution tool only analyzes the effects of nearby traces, regardless of the non-parallel traces that affect the other layers of the impedance. The on-site solution does not know the details before routing the routing width, but the above-mentioned pairing method can make this problem the smallest.
It is worth mentioning that the effect of the partial power planes is not complete. The outer circuit board is often packed with grounded copper wire after wiring, which helps to suppress EMI and balance plating. If only such measures are taken for the outer layer, the effect of the laminated structure recommended in this paper on the characteristic impedance is very small.
The effect of using a large number of adjacent signal layers is very significant. Some field-solving tools can not find the presence of copper foil because it can only check the printed wire and the entire level, so the analysis of the impedance is not correct. When there is metal on the adjacent layer, it is like a less reliable ground layer. If the impedance is too low, the instantaneous current will be large, which is a practical and sensitive EMI problem.
Another reason for the failure of the impedance analysis tool is distributed capacitance. These analysis tools generally do not reflect the effects of pins and vias (this effect is usually analyzed using an emulator). This effect can be great, especially on the backplane. The reason is very simple: the characteristic impedance can usually be calculated using the following formula:
√L / C
Where L and C are the inductance and capacitance per unit length, respectively.
If the pins are evenly arranged, the additional capacitance will greatly affect the calculation results. The formula will become:
√L / (C + C ')
C 'is the capacitance of the unit length of the pin.
If the connectors are connected in a straight line as on the backplane, the total line capacitance and the total pin capacitance except the first and last pins can be used. In this way, the effective impedance will be reduced, and may even drop from 80Ω to 8Ω. To find a valid value, divide the original impedance by:
√ (1 + C '/ C)
This calculation is important for component selection.
When simulating, consider the components and the capacitance of the package (and sometimes the inductance). Pay attention to two questions. First, the simulator may not correctly simulate the distributed capacitance; secondly, pay attention to the impact of different production conditions on incomplete and non-parallel traces. Many field-solving tools can not analyze stacking without full power or ground layer. However, if the ground layer is adjacent to the signal layer, then the calculated delay will be quite bad, such as capacitance, there will be the greatest delay; if a double-sided two layers are cloth with a lot of ground and VCC copper foil , This situation is even more serious. If the process is not automated, setting up these things in a CAD system will be very complicated.
EMC has a lot of factors, many of which are usually not analyzed, and even if it is analyzed, it is often too late after the design is complete. Here are some of the factors that affect EMC:
1. The slot of the power plane will form a quarter-wavelength antenna. For the metal containers need to open the installation slot of the occasion, should be used to replace the drilling method.
2. Inductive components. I have come across a designer who has followed all the design rules and has also made a simulation, but his circuit board still has a lot of radiation signals. The reason is: in the top there are two inductors placed in parallel with each other, constitute a transformer.
3. Due to the effect of the incomplete ground plane, the low impedance of the inner layer causes a large transient current in the outer layer.
The use of defense design can avoid most of these problems. First of all should make the correct stack structure and wiring strategy, so there is a good start.
There are no basic issues involved, such as network topology, signal distortion reasons, and crosstalk calculation methods; only some sensitive issues are analyzed to help readers apply the results from the EDA system. Any analysis depends on the model used, and the factors that are not analyzed can have an effect on the outcome. Too complicated as too imprecise to avoid excessive parameter changes (such as the width of the printed line, etc.), contribute to neat, consistent design.