The sensitivity of electronic equipment is getting higher and higher, which requires equipment anti-interference ability is also growing, so PCB design has become more difficult, how to improve the anti-jamming ability of PCB become one of the many key issues of concern to engineers. This article will introduce some of the tips for reducing noise and electromagnetic interference in PCB designs.
The following is after years of design summed up in the PCB design to reduce noise and electromagnetic interference 24 tips:
(1) can use low-speed chips do not have high-speed, high-speed chip used in key places.
(2) can be a string of resistance to reduce the control circuit up and down along the jump rate.
(3) as far as possible for the relay to provide some form of damping.
(4) Use the lowest frequency clock that meets the system requirements.
(5) The clock generator is as close as possible to the device using the clock. Quartz crystal oscillator housing to ground.
(6) with the ground clock will circle up, the clock line as short as possible.
(7) I / O drive circuit as close as possible to the printing edge, let it leave the printing plate as soon as possible. The signal into the printed circuit board to add filtering, from the high noise zone to the signal should also add filtering, while the use of string termination resistor approach to reduce the signal reflection.
(8) MCD useless side to be high, or ground, or defined as the output, the integrated circuit on the power supply to the end of the ground, do not vacant.
(9) idle Do not use the gate input do not vacant, idle unused op amp is the input terminal ground, negative input termination output.
(10) Printed board as far as possible, the use of 45-fold line without 90 fold line wiring to reduce the high-frequency signal external launch and coupling.
(11) printed circuit board by frequency and current switching characteristics of the partition, the noise components and non-noise components to be further away.
(12) single-sided and double-sided single-point power supply and single-point grounding, power lines, ground as thick as possible, the economy can withstand the use of multi-layer board to reduce the power supply capacity of the capacitive.
(13) clock, bus, chip select signal to stay away from I / O lines and connectors.
(14) analog voltage input line, the reference voltage side to try to stay away from the digital circuit signal lines, especially the clock.
(15) on the A / D class devices, digital parts and simulation part of the reunification do not even cross.
(16) The clock line is perpendicular to the I / O line than the parallel I / O line, and the clock component pin is far from the I / O cable.
(17) component pins as short as possible, decoupling capacitor pins as short as possible.
(18) The key lines should be as thick as possible and add protected areas on both sides. High-speed line to be short to straight.
(19) Noise-sensitive lines are not parallel to high-current, high-speed switching lines.
(20) Quartz crystal below and noise-sensitive devices below do not route.
(21) weak signal circuit, low frequency circuit around do not form a current loop.
(22) signals do not form a loop, such as unavoidable, so that the loop area as small as possible.
(23) a decoupling capacitor for each integrated circuit. Each electrolytic capacitor edge should be added a small high frequency bypass capacitor.
(24) with a large capacity of tantalum capacitors or cool capacitors without electrolytic capacitors for the circuit charge and discharge energy storage capacitor. When using a tubular capacitor, the housing is grounded.