(2) RMII interface

RMII interface is also commonly used between the 100 Gigabit Ethernet PHY chip and MAC interface. Table 5 is a hundred times the PHY timing parameter table, Table 6 and Table 7, respectively, is a MPU internal MAC timing parameter table.
High speed circuit design _PHY chip timing parameter table
Table 5 high-speed circuit design _ a PHY chip timing parameters table
High-speed circuit design _MPU MAC RX channel timing parameter table
Table 6 high-speed circuit design _ a MPU MAC RX channel timing parameter table
High Speed ​​Circuit Design _MPU Internal MAC TX Channel Timing Parameter Table
Table 7 high-speed circuit design _ a MPU MAC TX channel timing parameter table

The clock in the MPU does not support clock output in RMII mode, and PHY requires the clock signal to be input. The MPU works with the PHY in RMII mode and requires an external 50 MHz oscillator that meets both precision requirements to provide a clock reference for both parties.

To simplify timing analysis, the traces of the external oscillator to both the MPU and PHY can be designed to be equal, and the clock signal has exactly the same timing on the clock input pins of both.

Note: The general implementation of the isometric route is the serpentine line, but the equal length of the serpentine line does not necessarily mean waiting for a delay. Only when the snake line delay effect is equivalent or as close as possible to the straight line, the equal length means that the delay. In order to make the serpentine line with a similar delay effect of the line, the height of the serpentine line should be as small as possible, the opening of the serpentine line should be as wide as possible, that is, the shape of the wavy line is more favorable.

When the clock signal and other time to reach the two sides of the input and output pins, with the timing model shown in Figure 5, so only need to discuss the length of the data line.
High Speed ​​Circuit Design _ Shared Clock RMII Timing Model

Figure 5 high-speed circuit design _ shared clock RMII timing model

According to the above timing model, the following timing formula can be obtained:

(Tsetup) min + (Tco) max + (Tflt-data) max + Tjitter-clk + Tjitter-data <T (7)

(Tco) min + (Tflt-data) min - Tjitter-clk- ​​Tjitter-data> (Thold) min (8)

For the RXD, CRS_DV and RX_ER signals, the group of signals is sent by the PHY to the MPU. According to equations (7) and (8), the minimum Tco time is considered to be equal to the Thold time for simplicity:

-1 flt-data <2

Trace time can not be negative, assuming that the alignment is located on the PCB surface, the material is FR-4, then:

Lflt-data <31.75CM

For TXD, and TX_EN signals, the group of signals is sent by the MPU to the PHY. According to equations (7) and (8),

-0.5 flt-data <3

Trace time can not be negative, assuming that the alignment is located on the PCB surface, the material is FR-4, then:

Lflt-data <47.625CM

For the RXD, CRS_DV and RX_ER signals, the group of signals is sent by the PHY to the MPU. Assuming that the data line length is 0, the data line delay is 0ns. At this time, the minimum settling time of the signal on the MPU side is 20-14 = 6ns and the minimum hold time is 3ns. The minimum settling time required for the MAC side is 4ns and the minimum hold time is 2ns. It can be seen that the maximum length of the data line can be 2ns, and the establishment time and hold time of the signal on the MAC side are 4ns and 5ns respectively, which meet the timing requirements. So the length of the long line can be 31.75CM.

For TXD and TX_EN signals, the group of signals is sent by the MPU to the PHY. Assuming that the data line length is 0, the data line delay is 0ns. At this time, the minimum settling time of the signal on the PHY side is 20-13 = 7ns and the minimum hold time is 2ns. The minimum settling time required for the MAC side is 4 ns and the minimum hold time is 1.5 ns. It can be seen that the maximum length of the data line can be 3ns, and the establishment time and hold time of the signal on the MAC side are 4ns and 4.5ns respectively, which meet the timing requirements. So the length of the alignment can be up to 47.625CM.

(3) RGMII interface

RGMII interface is the most commonly used Gigabit Ethernet PHY chip and MAC interface, Table 8 and Table 9 are a Gigabit PHY chip and a MPU internal Gigabit MAC TX channel timing parameter table. The RGMII-ID function is enabled for the gigabit MAC. To simplify the wiring operation, the PHY internal bidirectional enable the RGMII-ID function. The related timing parameter is the RGMII-ID function enabled value. Note that the RGMII timing is DDR mode.
High Speed ​​Circuit Design _ Gigabit PHY Chip TX Channel Timing Parameter Table
Table 8 high-speed circuit design _ a Gigabit PHY chip TX channel timing parameters table
High speed circuit design _MPU within the Gigabit MAC channel timing parameter table
Table 9 high-speed circuit design _ a MPU Gigabit MAC channel timing parameters table

This group of data from the MAC to PHY, for the source clock synchronization. In the case where the internal delay of the PHY side is enabled, the minimum value of the data receiving and holding time is -0.9ns and 2.7ns respectively. In the worst case, the minimum settling time for the MPU to send data is -0.5ns and the minimum hold time is 4-0.5 = 3.5ns. Therefore, the clock line and data lines are the simplest wiring method.

Assuming that the data signal has a positive delay relative to the clock signal, the data can be clocked up to + 0.4 ns in order to ensure that the minimum settling time of the PHY terminal is -0.9 ns. In the worst case, there are:

PHY side of the data relative to the clock delay of -0.9ns, that is, the establishment of time is -0.9ns;

Since the data exists independently of less than 4-0.5-0.5 = 3ns, the hold time is never less than 3.5ns;

At this point, the system as a whole to meet the timing requirements, the data line can be longer than the clock line 6.35CM.

Assuming that there is a negative delay for the data signal relative to the clock signal, in order to ensure that the minimum hold time of the PHY terminal is 2.7 ns, the data can be set to a maximum clock delay of -0.8 ns since the data is not shorter than 3.5 ns with respect to the clock edge. In the worst case, there are:

PHY side of the data relative to the clock delay of 0.3ns, that is, the establishment of time is 0.3ns;

PHY side data retention time is 3.5-0.8 = 2.7ns;

At this point, the system as a whole to meet the timing requirements, the clock line can be longer than the data line 12.7CM.

Table 10 and Table 11, respectively, the Gigabit PHY chip and the MPU internal Gigabit MAC TX channel timing parameter table. The timing analysis of this group is relatively simple, it is easy to analyze the data traces on the clock alignment delay can be ± 0.2ns, for the surface traces, FR-4 material, converted into the length of the line is 3.175CM.
High Speed ​​Circuit Design _ Gigabit PHY Chip TX Channel Timing Parameter Table
Table 10 high-speed circuit design _ a Gigabit PHY chip TX channel timing parameters table
High speed circuit design _MPU within the Gigabit MAC channel timing parameter table
Table 11 high-speed circuit design _ a MPU Gigabit MAC channel timing parameters table

Figure 6 is the RGMII timing model, that is, DDR mode timing diagram. Equations (9) and (10) are the corresponding set-up time and hold-time constraint formulas. In the formula, Tstrobe - data represents the transmission delay of the strobe signal relative to the data signal; Tdata -strobe represents the transmission delay of the data signal relative to the strobe signal.
High - speed circuit design _RGMII timing diagram
Figure 6 high-speed circuit design _RGMII timing model diagram

(Tsetup) min <(Tco) min + (Tstrobe - data) min - Tjitter-data - Tjitter-strobe (9)

(Thold) min <(Thold-data) min + (Tdata -strobe) min - Tjitter-data - Tjitter-strobe (10)
The corresponding parameters in the RGMII timing parameter table are brought into equations (9) and (10)

For RX channels:

Tdata-strobe <0.4

Tstrobe-data <0.8

That is equivalent to:

Ldata-Lstrobe <6.35CM

or

Lstrobe-Ldata <12.7CM

It can be seen that the formula is consistent with the theoretical analysis. The TX channel can be calculated using a similar method.

(4) SPI interface

For cost factors, more and more consumer electronics use SPI FLASH as a memory. SPI communication speed is getting higher and higher. At present, most MPUs can support more than 100M SPI communication speed and support multiple I / O communication.

(11), the formula (12), the formula (13), and the formula (14) are the data read timing and the data write timing of the SPI in mode 1, respectively, and the timing of the SPI communication is different from that described above. ) Is the corresponding timing constraint formula. It can be seen that the formula will change due to the different timing relationships. Therefore, the timing analysis to specific issues specific treatment.
High Speed ​​Circuit Design _SPI Mode 1 Write Timing
Figure 7 high-speed circuit design _SPI mode 1 write timing

High speed circuit design
High speed circuit design _SPI mode 1 read timing
Figure 8 High-speed circuit design _SPI mode 1 read timing

High speed circuit design

3. Conclusion
The key point in timing analysis is that it is necessary to have a clear understanding of the timing relationship being analyzed and to have a deep understanding of the timing of the current object. Second, the timing analysis should be specific to the specific analysis, there is no so-called universal timing formula. Sometimes, relying solely on theoretical analysis or simply relying on the relationship between the formula is not necessarily able to solve the problem, but to the combination of the two.

For high-speed signal wiring, there is "equal length" that many engineers believe that as long as all the lines as long as possible, it must meet the timing requirements. In fact, this is a false understanding, this example of the case to clearly prove this point. Only those clocks and data from the same device issued by another device to accept, and the sender of the establishment time and hold time just to meet the needs of the receiver, the "equal length" is considered a lazy way. In addition, especially those that are driven by a one-way clock, sampling bi-directional data or reverse data must be specifically analyzed. Of course, for PC such general equipment, because the motherboard design needs to be compatible with different manufacturers of memory, then the alignment design is equal is indeed a reasonable design.

The public clock system samples bi-directional data using a one-way clock signal, so there are double limits, and the two sets of constraints restrict the alignment not only to the trace length limit, but also the total length of the trace. The source synchronous clock system uses a clock that is the same as the data, so there is only a single limit, so that the trace has only a difference limit without a total length limit.

In general, for the SPI interface, MII interface, shared clock RMII interface or SDRAM signal, the trace should be as short as possible. For DDR SDRAM signals and RGMII and other DDR timing interface, in most cases, the group is always a simple and fast method.