Enhanced Boundary Scan Unit

Boundary scan is a widely used test technique that requires a boundary scan unit to be configured between the input and output pins and the internal core logic. Boundary scan test technology can efficiently test kernel logic and interconnect. Figure 4 shows the standard boundary scan unit (BSC) with the traditional shift and update nodes. Mode_1 causes the unit to be in test mode. The data is shifted by the shift register (Shift-DR state) during the scan operation. The test mode scanned by the scan input port (TDI) into the boundary scan unit is used in parallel under the Update-DR state (UpdateDR signal). The boundary scan unit connected between the internal logic and the output pin can capture the circuit response in parallel and scan the output through the scan output port (TDO). The JTAG standard (IEEE 1149.1) can be used to test the interconnection of the adhesion, open circuit and short circuit fault situation, which is through the "EXTEST" instruction to achieve, in this instruction under the operation of the TAP controller using BSC from the interconnection of kernel logic. But the purpose of this test is not to test the signal integrity of the interconnection. In order to test the signal integrity of the interconnect, a little improvement in the standard architecture is required.

Monitor BSC (OBSC)

It is advisable to place a new BSC using the ILS unit on the receiving side of the interconnect, as shown in Figure 5, which is called the monitoring BSC (OBSC). ILS is added to the receiving side units, which are capable of capturing signals with noise and delay at the interconnection ends. If it receives a signal with integrity problems (such as latency damage), it outputs a pulse at the output and sets the trigger to "1". OBSC has two modes of operation:

1) Integrity mode (SI = 1): Select signal F. The captured integrity data is captured by the scan chain in each Shift-DR state and used for final evaluation.
2) Normal mode (SI = 0): In this mode ILS is isolated, and each OBSC is used as a standard BSC.
During the scan output, we need to capture the output F signal and send it to FF1. In this case sel should be set to 0, so SI and ShiftDR should be 1 and 0, respectively. When the scan output process is started, D1 is transferred to Q1 and used as the TDI for the next cell. The signal integrity information is captured by FF1 after the ILS flip-flop is reset. After sending the F value to Q1, the scan chain must be formatted. During the Shift-DR state of this example, the TDI input must be connected to FF1. Therefore, the sel must be set to 1 (SI = '1', ShiftDR = '1') to isolate the ILS path. As shown in Figure 5, SI and ShiftDR need to be performed or operated to select and transmit signals F to D1 and generate scan chains for scan output.
Figure 6 shows the relationship between sel and SI and ShiftDR. As shown in the figure, in the Capture-DR state, the signal F is selected and the scan chain is formatted in the Shift-DR state and the output data is scanned according to the number of lines being tested. Table 1 shows the truth table of the signal sel. Only one control signal (ie SI) is generated by the new instruction. There are three ways to perform monitoring of signal integrity information: 1) Read out after applying each test pattern; 2) Read out after applying the test pattern subset; 3) Read the test mode once. Which method is chosen depends on the acceptable time cost. The first method is very time consuming, but it can display the integrity information of each interconnection as much as possible. The third method is very fast, but the integrity of the information is relatively small, because it can only get which mode or which model subset of the integrity of the fault caused by the information, can not know the type of failure. Method 2 helps the user to strike a balance between test time and accuracy.

Test architecture

Figure 7 shows the overall test architecture for small SoCs where the JTAG inputs (TDI, TCK, TMS, TRST, and TDO) are used without any modification. But defines a new instruction that is used primarily to read the test results in the signal integrity test. As can be seen from Figure 7, only each interconnected receiver unit is changed to OBSC. For bidirectional interconnection, the OBSC unit is used for both sides between Core j and Core1. The other units are standard BSC and appear in the scan chain during the signal integrity test mode. The role of ILS is independent, and no special control circuitry is required to control the timing of such cells. The integrity information displayed by F is scanned to determine the problematic interconnection.

1. EX-SITEST instruction

For the new test architecture, it is recommended to add a new instruction EX-SITEST to the IEEE 1149.1 instruction set. This instruction is similar to the EXTEST instruction, but adds the control signal SI. In the Update-IR state, this instruction is decoded and generated (SI_1). The output unit is used as the standard BSC and the input unit is used as the OBSC. The signal F is captured in the Capture-DR state and the output is shifted out at the speed of each clock cycle during the Shift-DR state. In this example, the TAP controller state does not change, but some changes are required when the instruction is decoded. The data flow of the EX-SITEST instruction that exists between the cores is shown in Figure 8.

2. Test process
The TAP controller IR is first loaded by the EX-SITEST instruction, and then all test patterns are applied to the interconnection while the ILS unit captures the signal at the end of the interconnect and detects all possible faults. After the test application has finished, the result stored in the ILS unit FF must be read. The monitoring process can take advantage of one of three methods. For example, use method 3, apply all test patterns, and then read the integrity of information at once.

3. Test data compression
In the traditional Boundary Scanning Architecture (BSA), the test pattern is a scan and is applied to the interconnection. For example, in an n-bit interconnect with a maximum intrusion (MA) failure model, 12 test patterns are applied to each victim line, requiring a 12n clock when the test pattern is applied to the victim line. The number of total clocks (number of test applications) is 12n2 between the n interconnections. Of course, MA is a simplified model. If you use a more complex model or SoC with a large number of interconnection, the number of test patterns will surge, then compression is necessary. This article describes a simple and effective compression technique for increasing the boundary scan architecture. Due to limited space, this article can only be a brief introduction, to illustrate the flexibility of the enhanced JTAG architecture.
This compression technique has two key points. First, our approach is a simple lossless compression method that builds a compressed bit stream by determining the maximum similarity between adjacent two patterns and covering them. Second, since this compression method is non-destructive and does not reorder the pattern, no additional decompression hardware is required. And only use the automatic test equipment (ATE) to control the JTAG TMS control input to perform the decompression process. When the test pattern is generated, there are often a number of insignificant patterns that appear in the test pattern set. The same is true for the pattern of signal integrity, especially when regional metrics are taken into account (limiting the development model space). In any case we assume that the test set consists of the same length that contains an unimportant pattern. Figure 9 expresses our basic compression idea, that is, the use of unimportant parts to cover as many as possible to complete the two modes Vi and Vj (length is 1_16) compression.

Test data compression

Summary of this article

In this example, the compressed data (Vi, Vj) requires only 21 clocks for the scan input, while the uncompressed data requires 16 + 16 = 32 clocks. It is important to note that in order to decompress the specified data stream, we need a pattern of a number (such as di and dj in this example) to construct (unzip) the pattern. For the purpose of boundary scan testing, these quantities are the number of shifts (ie, clocks) required to update the contents of the BSC unit. We assume that the ATE stores the decompressed data (d value is 0 ≤ d ≤ 1) and the data activates the TMS (test mode selection) signal after d clocks when the input bit stream is scanned. The TMS signal then causes the TAP controller to generate correct control instructions (eg EX-SITEST) for signal integrity testing. So we do not need additional decompression hardware in our architecture.