The concept of power integrity
Power Integrity (PI, Power Integrity) is a stable and reliable power distribution system (PDS) for board-level systems. In essence, is to make the system at work, power, ground noise is effectively controlled in a wide frequency range for the chip to provide sufficient energy, and fully inhibit the chip when the work caused by voltage fluctuations, radiation and crosstalk.
With the development of ultra-large-scale integrated circuit technology, the chip working voltage is getting lower and lower, and work faster and faster, more and more power consumption, board density is getting higher and higher, so the power supply system in the whole The stability of the working band is more demanding. The level of power integrity design directly affects the performance of the system, such as machine reliability, signal to noise ratio and bit error rate, and EMI / EMC and other important indicators. Board-level power supply channel impedance is too high and synchronous switching noise SSN over the General Assembly to bring serious power integrity problems, which will give the device and system stability of the work of a fatal impact. PI design is through a reasonable flat capacitor, discrete capacitors, planar segmentation applications to ensure that the board-level power supply channel impedance to meet the requirements to ensure that the board-level power quality meet the device and product requirements to ensure signal quality and devices, product stability.
Power supply integrity PI and signal integrity SI interaction: from the entire simulation field, the beginning we all focus on the signal integrity, but in fact the power integrity and signal integrity is mutual influence each other The Power supply, ground plane in the power supply at the same time to the signal line to provide a reference loop, directly determine the return path, thus affecting the signal integrity; the same signal integrity of the different processing methods will also bring different impact to the power system, thus affecting the power The integrity of the design. So it is very useful for the integrity of the power supply and the integrity of the signal. Design engineers have mastered the signal integrity design method, to enrich the power integrity design knowledge is necessary.
Power integrity research content: power integrity simulation of many, but the main aspects are as follows:
1: Board-level power channel impedance simulation analysis, based on the full use of planar capacitance, through simulation analysis to determine the number of bypass capacitors, types, location, etc., to ensure that the board-level power supply channel impedance to meet the stability requirements of the device.
2: Board-level DC voltage drop simulation analysis to ensure that the board-level power supply to meet the device voltage drop limit requirements.
3: Board-level resonance analysis, to avoid board-level resonance on the power quality and EMI fatal effects.
Power distribution system
Power distribution system
Power distribution system (PDS): The figure is a classic power distribution system characteristics map, I believe we are more familiar with. From this figure, we can divide the entire power band into several parts. In the low frequency band, the power supply noise mainly depends on the power conversion chip VRM to filter. In the frequency range of several MHZ to several hundred MHZ, the power supply noise is mainly filtered by the board-level discrete capacitance and the PCB ground plane. In the high-frequency part, the power supply noise is mainly by the PCB power ground plane and the chip's high-frequency capacitor to filter. When we are doing simulation, the low frequency and high frequency part of the simulation accuracy is not accurate, the real meaningful band is still a few MHZ to several hundred MHZ this band.
Target impedance Ztarget
The target impedance is a useful but inaccurate standard in power integrity simulations.
Target resistance
Where: Ztarget target impedance
Power Supply Voltage is the operating voltage
Allowed Ripple is the allowable operating voltage ripple factor
Current is the operating current, and this value is currently replaced by 1/2 of the maximum current
We all know that power testing, mainly testing ripple, noise, but the industry is still difficult to software through the time domain ripple noise simulation (some large companies have passed the test to build the chip noise model, and then use this Model direct simulation, the result is power noise, but is still in the exploratory stage, there is no promotion to use), but the simulation power distribution system power supply impedance, their relationship can be linked by V = R / I. So if the simulation curve is still simulated, test and simulation can not form a closed loop.
In the measure of whether the impedance curve to meet the requirements of the time, the use of the target impedance of the standard, but think about it, this standard is still a lot of problems, such as: how much the current here? The actual board power consumption is a dynamic power consumption that is not changed. In the entire frequency band of the board, the use of a unified target impedance value, it is certainly unreasonable, should be the various bands, the standard is not the same.
Although these problems exist, but this standard is still very useful, you can measure the power plane through this standard is good or bad. As the current timing calculation, we are basically through the formula to calculate the timing, is the so-called static timing analysis. Although this static timing analysis is not thoughtful about power fluctuations, ISI, SSN, etc., that is to say the calculation results are not accurate, but used to measure the timing of the interface is still very useful. Therefore, the target impedance is a useful and inaccurate standard.
Capacitance is not just capacitance: when the frequency is high, the capacitor can no longer be seen as an ideal capacitor, but should take full account of its parasitic parameters, the capacitance of the parasitic parameters of ESR, ESL. The series of RLC circuits resonate at f. The curve is shown below. In the figure, f is the series resonant frequency (SRF), before f is capacitive, and after f, then the sensibility, quite an inductance, so in the choice of filter capacitor, the capacitor must be in the resonant frequency before.
Series resonant frequency
In the simulation, because the current VRM model is basically not accurate, low-frequency filter by DC / DC power conversion chip to complete, generally below 300K low-frequency impedance curve is not accurate. The upper limit of the frequency range generally takes the cutoff frequency of the signal fknee = 0.35 / Trrise, where Trise is the signal rise time.
But also to understand that if you just do board-level power integrity simulation, up to 1G can be considered, because more than 1G later, rely on the chip's internal capacitance to filter, do board-level simulation, no chip internal Of the model, so the high-frequency part of the simulation is not accurate. Of course, if you have the information inside the chip, you can also use SIWAVE and other software to do DIE-PACKAGE-BOARD co-simulation, high-frequency part of the accurate.
So many cases, low-frequency simulation of negative feedback, high-frequency simulation of the chip capacitor, we do not take the simulation results as an absolute value, it can be regarded as a relative value, through the decoupling capacitor selection and placement, Power and ground plane segmentation and other methods to optimize the impedance. So, do the simulation when the need for flexible use.