In a high-speed printed circuit board (PCB), vias have been criticized for reducing signal integrity performance. However, the use of vias is unavoidable. On a standard PCB board, the components are placed on the top layer, while the differential pairs are trapped in the inner layer. The inner layer of electromagnetic radiation and the crosstalk between the pair and the lower. The vias must be used to connect the components on the PCB plane to the inner layer. Fortunately, a transparent vias can be designed to minimize the impact on performance.

1. The basic knowledge of the through-hole structure

Let's start by checking the simple vias that connect the top transmission line to the inner layer. Figure 1 is a 3D diagram showing the via structure. There are four basic components: signal vias, vias, pits, and vias.

The via is a metal cylinder that is plated outside the through-hole between the top and bottom layers of the circuit board. Signal vias connect the transmission lines on different layers. The over-hole pile is an unused part of the hole. The via pads are rounded gaskets that connect vias to the top or internal transmission lines. The isolation disc is an annular gap in each power supply or ground layer to prevent short circuit to the power supply and ground plane.
A single hole of the 3D map
Figure 1: 3D view of a single vias
through-hole-foundation-knowledge-in-pcb-design 1
2. Electrical properties of the via element

As shown in Table 1, let's take a closer look at the electrical properties of each via element.
The electrical properties of the via element
Table 1: Electrical properties of the via elements shown in Figure 1
through-hole-foundation-knowledge-in-pcb-design 2
A simple via is a series of π-type networks consisting of a capacitance-inductance-capacitance (C-L-C) element consisting of two adjacent layers. Table 2 shows the effect of the via size.
The intuitive effect of the hole size
Table 2: Intuitive effects of via size
through-hole-foundation-knowledge-in-pcb-design 3
By balancing the size of the inductor and the parasitic capacitance, it is possible to design vias with the same characteristic impedance as the transmission line, and thus do not have a special effect on the circuit board operation. There is no simple formula to convert between the via size and the C and L components. The 3D Electromagnetic (EM) field solution program predicts the structural impedance based on the size used in the PCB layout and routing. By repeating the adjustment of the structure size and running the 3D simulation, the via size can be optimized to achieve the required impedance and bandwidth requirements.

3. Design a transparent differential via

When implementing differential pairs, line A and line B must be highly symmetrical. These are traces in the same layer, and if a vias is required, holes must be made in the vicinity of the two lines. Since the two vias of the differential pairs are very close, an oval disc that is shared by the two vias can reduce the parasitic capacitance rather than using two separate spacers. The ground vias are also placed next to each vias, so that they can provide a ground return path for the A and B vias.

Figure 2 shows an example of a ground-to-signal-ground-ground (GSSG) differential via structure. The distance between two adjacent vias is called the via spacing. The smaller the hole spacing, the more the mutual coupling capacitance.
Use a GSSG differential via on the back hole
Figure 2: GSSG differential vias with back drills
through-hole-foundation-knowledge-in-pcb-design 4
Do not forget that when the transfer rate exceeds 10Gbps, the hole residue will seriously affect the high-speed signal integrity. Fortunately, there is a back-hole PCB manufacturing process that can be drilled on unused through-hole cylinders. Depending on the manufacturing process tolerances, the backside bore removes the unused vias and minimizes the residual piles below 10 mils.

The 3D EM simulator is used to design the differential vias according to the required impedance and bandwidth. This is a repetitive process. This process repeats the adjustment of the via size and runs the EM simulation until the desired impedance and bandwidth are achieved.

4. How to verify performance

The differential via design shown in Figure 2 has been built and tested. The test sample includes a pair of differential lines on the top layer, followed by a differential vias to the internal differential line, and then the second pair of differential vias are again connected to the top of the spherical pin grid array package (BGA) ground pad. The total length of the signal path is approximately 1330 mils. I measured the differential impedance with a differential time domain reflectometer (TDR), measured the bandwidth with a network analyzer, and measured the data eye with a high-speed oscilloscope to understand its effect on the signal. Figures 3, 4 and 5 show impedance, bandwidth and eye diagrams, respectively. The left graph is the result of the test when the back hole is used, and the right is the test result without the back hole. In the bandwidth diagram in Figure 5, we can clearly see that the backside drilling is essential for achieving high performance at data rates greater than 10 Gbps.
TDR Impedance Bode Chart
Figure 3: TDR Impedance Bode (left: using backside drilling, ZDIFF is approximately 85Ω; right: no back hole drilling, ZDIFF is approximately 58Ω)
Frequency response
Figure 4: Frequency response (left: 12.5GHz when the insertion loss is about 3dB; right: 12.5GHz when the insertion loss is greater than 8dB)
25Gbps when the data eye
Figure 5: Data view at 25Gbps (left: when the back hole is used, the data eye is open; right: the data eye is closed when no back hole is drilled.)