2. Timing analysis examples

(1) MII interface

MII interface is the most commonly used 100M Ethernet PHY chip and the interface between the MAC, Table 1 and Table 2, respectively, a hundred trillion PHY chip and an internal MAC MAC channel timing parameters table.
High Speed ​​Circuit Design _PHY Chip RX Channel Timing Parameter Table
Table 1 high-speed circuit design _ a PHY chip RX channel timing parameter table
High-speed circuit design _MPU MAC RX channel timing parameter table
Table 2 high-speed circuit design _ a MPU MAC RX channel timing parameters table

It can be seen from the table that the MAC side requires RXD, RX_DV and RX_ER signals to establish and hold the RX_CLK signal at a minimum of 8ns, that is, the actual setup and hold time shall not be less than 8ns. Assuming that the delay of RXD, RX_DV and RX_CLK signals from PHY side to MAC side is exactly the same,

The transmission clock cycle is 40ns;

The minimum settling time is 40-tval = 12ns;

The minimum hold time is thold = 10ns;

The minimum settling time and hold time is 22ns;

Assuming there is a delay in the RX_CLK signal for the RXD, RX_DV, and RX_ER signals, there are two extreme cases:

When the delay time leads to the minimum requirement of establishment time, that is, when the relative delay is + 4ns, the establishment time is 8ns on the MAC side and the holding time is 14ns;

When the delay time leads to the minimum requirement, that is, when the relative delay is -2ns, the establishment time is 14ns and the hold time is 8ns.

Assuming that the MII interface is traced on the PCB surface and the PCB board is FR-4, the signal transmission speed is about 160 ps / inch. Based on the above two cases, it can be concluded that the trace length relationship of RXD, RX_DV and RX_ER relative to RX_CLK is: RXD, RX_DV and RX_ER traces relative to RX_CLK can be short: 2000/160 * 2.54 = 32CM; visible to the RXD, RX_DV and RX_ER traces relative to RX_CLK can be long: 4000/160 * 2.54 = 63CM; , For the MII RX channel signal, you can not consider the equal length.

Note that timing relationships do not represent the need to consider reflection problems. When the propagation and return delay of the signal on the trace is longer than the rise time of the signal, it is necessary to consider whether terminal impedance matching is performed to suppress the reflection.

The following formula is used to calculate the pros and cons of comparative theoretical analysis and formula. To simplify the calculation, ignore the jitter factors Tjitter-clk and Tjitter-data in equations (1) and (2), the correlation formula becomes:

(Tset) min + (Tco) max + (Tflt-data - Tflt-clk) max <T (5)

(Tco) min + (Tflt-data - Tflt-clk) min> (Thold) min (6)

The parameters in Table 2 and Table 3 are brought into equations (5) and (6)

10 - (Tco) minflt-data - Tflt-clk <4

Since the PHY chip parameter does not give the parameter (Tco) min, the formula does not give the final result. Since the maximum output delay of the PHY chip is 28ns and the shortest hold time is 10ns, assuming that (Tco) min is 12ns, then:

-2flt-data - Tflt-clk <4

Can be decomposed into:

Tflt-data - Tflt-clk <4

Tflt-clk -Tflt-data <2

Converted into length is:

Lflt-data - Lflt-clk <63cm <p = "">

Lflt-clk -Lflt-data <32cm <p = "">

It can be seen that the use of formula analysis sometimes subject to incomplete parameters of the constraints, then need to infer the parameters according to other parameters required. Comparative analysis and formula method, we can see: analysis method is more complicated, need to carefully analyze the timing relationship, and the formula is very fast.
However, the formula method is sometimes subject to the parameters of the constraints, not a comprehensive conclusion. In practice, two methods should be used in combination.

The timing of the TX channel between the PHY chip and the MAC is analyzed below. Table 3 and Table 4, respectively, is the 100M PHY chip and MPU internal MAC TX channel timing parameter table.
High speed circuit design _PHY chip TX channel timing parameter table
Table 3 high-speed circuit design _ a PHY chip TX channel timing parameters table
High Speed ​​Circuit Design _MPU Internal MAC TX Channel Timing Parameter Table
Table 4 high-speed circuit design _ a MPU MAC TX channel timing parameters table

Using the formula for calculation, in order to simplify the jitter factors Tjitter-clk and Tjitter-data in equations (3) and (4), the correlation formula becomes:

(Tset) min + (Tco) max + (Tflt-data) max + (Tflt-clk) min <T

(Thold) min <(Tco) min + (Tflt-data) min + (Tflt-clk) max

Into the parameters of the parameters of the table, simplified to get:

Lflt-data + Lflt-clk <47.625CM

Assuming that the MII trace is on the PCB surface, the PCB material is FR-4 and the trailing speed is 160 ps / inch. Based on the above analysis, it can be concluded that the sum of TXD, TXEN and TXCLK can not be greater than 47CM. In actual wiring, this group should be as short as possible. The shorter the trace, the more data set up, the less time to keep. In this example, the MAC side allows a hold time of 0 ns.