The loss of signal integrity in interconnections is a critical issue for hundreds of gigahertz complex SoC, so there are often some special ways to solve this problem in design and testing. This paper describes how to use the on-chip mechanism to extend the JTAG standard to include interconnection signal integrity testing, which uses the JTAG boundary scan architecture to test high-speed system-on-chip (SoC) interconnects on the occurrence of delay damage.

The loss of signal integrity in interconnections is a critical issue for hundreds of gigahertz complex SoC, so there are often some special ways to solve this problem in design and testing. We believe that integrity loss (sometimes referred to herein as integrity failure) occurs when voltage distortion (noise) and delay damage (offset) exceed acceptable thresholds. This threshold depends on the manufacturing process used. There are many unpredictable causes of this failure, including: 1. Generating parasitic values ​​such as transistor size, transconductance, threshold voltage, parasitic resistance / inductance / capacitance values, and the like, as well as transmission line effects such as crosstalk , Overshoot, reflection, electromagnetic interference, etc., these problems are difficult to analyze and the manufacturing process will have a change between the interconnection between the coupling effects (such as coupling capacitance and mutual inductance). 2. SoC switch in the switch at the same time caused by ground rebound, usually resulting in noise margin changes.

The signal integrity of the system-on-chip interconnect is tested using a boundary scan method

Integrity failure model

The most widely used model is the largest intrusion (MA) failure model, which is a simplified model used by many researchers to perform crosstalk analysis and testing of long distance interconnects. As shown in Fig. 1, the model assumes that the signal transmitted on the V (victim) line is affected by the signal / change on another adjacent A (intruder side) line. This coupling effect can be summarized by the general coupling element Z. In general, the consequences of this effect are noise (causing ringing and functional errors) and delays (causing performance degradation).

This article uses the same model. However, we need to emphasize that there is still controversy over what model will cause the greatest loss of integrity. It is clear that the traditional MA model only takes into account the capacitive coupling (couplingC), all the invading parties simultaneously make the same jump while the victim either remains the same (for the largest ringing) or makes the opposite jump (for the largest Delay). When the mutual inductance works, some researchers use other methods (pseudo-random or constant) to produce the test pattern to form the greatest integrity loss. Although we still use the MA model, the test method does not depend on the test pattern. In this paper, it is assumed that the test pattern has been determined, and the reader can see how they are efficiently fed through the enhanced JTAG architecture.

Integrity loss sensor (ILS) unit

As the integrity loss in the gigahertz chip has received more and more attention, some researchers have developed a series of on-chip sensors. Many of these integrity loss sensors (ILS) are based on the amplifier circuit, which can detect voltage damage and delay thresholds. The BIST (built-in self-test) structure using the D flip-flop is recommended for the detection of the propagation delay deviation. During the test mode, the op amp to be tested is placed in a voltage follower configuration to detect the slope deviation or is placed in the comparator configuration to detect the propagation delay of the signal.

Integrity loss sensor (ILS) unit

The use of IDDT and boundary scan methods is a test technique to solve bus interconnection defects. In this case a built-in sensor is integrated into the system. The sensor is an on-chip current mirror that can convert the scattered charge into the relevant test time. Noise detectors (ND) and offset detector (SD) units are based on improved crosstalk PMOS differential sense amplifiers, so the price is very cheap. These units are close to the end of the interconnect and the actual signal and noise are sampled. Each time the noise or offset is above the acceptable limit, these units produce a 1 to 0 transition and are stored in the trigger for further analysis.
Someone has provided a higher-priced but more accurate circuit that can test jitter and offset in picosecond, a circuit called EDTC that avoids sampling signals and issues test information through low-speed serial information. When the cost is not a problem, the concept of accurate signal monitoring can be accepted by researchers, and even produce the idea of ​​on-chip oscilloscope.

ILS unit

Although any ILS sensor can be used for integrity loss testing, but for the sake of simplicity, economic and experimental purposes, we have also developed their own ILS unit. The circuit and function of this unit will be briefly described below, but the detailed functions of this unit are beyond the scope of this article.

ILS unit

The ILS used in this example is a time-delay sensor as shown in Fig. The acceptable delay range (ADR) is defined as the start of the trigger clock edge, and all output transitions must occur during this time. The test clock is used to create a window to determine the acceptable offset range. If the transition of input signal a occurs within the time when b is logic '0', then signal a is within an acceptable delay range. Any jump that takes place within b for logic '1' is passed through the transfer gate to the XNOR gate, which is implemented using dynamic precharge logic. Adjust the inverter 1 according to a reasonable delay range. The output c is 1 when there is a signal transition in the time b is 1, and until b becomes 0, the next precharge cycle is started. The output is used to trigger a trigger. Figure 3 shows the input signal a has two signal transition unit SPICE simulation, using 0.18μm technology to achieve. The first signal transition occurs at 0.2ns, where b is 0 and the output remains at 0. The second signal transition occurs at 3.5 ns, where b is 1, and output c remains at 1 until b becomes 0 due to an acceptable delay period. The delay sensor also detects a crossover error caused by crosstalk. The pulse can be fed back to the trigger to store the delay event for further reading / analysis.